The present invention relates to a semiconductor integrated circuit device. Particularly, the present invention is effective in a semiconductor integrated circuit device such as for liquid crystal for a liquid crystal display panel, for a thermal head printer, and for a quartz clock.
The present invention relates to a semiconductor integrated circuit of an insulated gate field effect type and a method of manufacturing thereof. More particularly, the present invention relates to an IC such as a driver IC for driving liquid crystal, for driving a resistor for heat sensitive paper, and the like, and an IC for a quartz clock and the like.
In a conventional N type semiconductor device indicated in FIG. 2 (a plane view), a gate electrode 7 is provided in the vicinity of the surface of a P type semiconductor substrate 1 through a gate insulating film. An N type drain region 4 is provided in a region adjacent to a part of the gate electrode 7 in the vicinity of the surface of the P type semiconductor substrate 1 through a part of the gate insulating film. An N type source region 3 is provided in a region adjacent to a part of the gate electrode 7 opposing the part of the gate electrode 7 through the part of the gate insulating film. A P type high doped impurity region 9 for earthing to the substrate is provided near the surface of the P type semiconductor substrate 1 apart from N type source 3 and drain region 4. A P type lightly doped impurity region 17 for device isolation surrounding a gate electrode (channel region) sandwiched between the N type drain region 4 and the N type source region 3 and surrounding the N type drain region 4 and the N type source region 3 is provided. And a thick oxide film for device isolation is provided an the P type lightly doped impurity region 17 for device isolation.
Further, in a conventional P type semiconductor device, an N type lightly doped impurity diffusion region 2 is provided in the vicinity of the surface of a P type semiconductor substrate 1. A gate electrode 7 is provided in the vicinity of the surface of the N type lightly doped impurity diffusion region 2 through a gate insulating film. A P type drain region 6 is provided in a region adjacent to a part of the gate electrode 7 in the vicinity of the surface of the N type lightly doped impurity diffusion region 2 through a part of the gate insulating film. A P type source region 5 is provided in a region adjacent to a part of the gate electrode 7 opposing the part of the gate electrode 7 through the part of the gate insulating film. An N type lightly doped impurity region 2 for device isolation surrounding a gate electrode 7 sandwiched between the P type drain region 6 and the P type source region 5 and the P type drain region 6 and the P type source region 5 is provided. A N type highly doped impurity region 10 for earthing the voltage is provided on the surface near the N type lightly doped region 2. And a thick oxide film for device isolation is provided on the N type lightly doped impurity region 2 for device isolation.
Further, in a conventional method of manufacturing a semiconductor integrated circuit device (not shown in Fig.), a plurality of CMOS field effect transistors are integrated by a step of forming an N type lightly doped diffusion region in the vicinity of the surface of a P type semiconductor substrate by lithography and ion implantation and thermal diffusion, a step of forming a thick oxide film for device isolation and a lightly doped impurity region for device isolation by LOCOS, a step of forming a gate oxide film in the vicinity of the surface of an active region of the P type semiconductor substrate and of the N type lightly doped diffusion region, depositing polysilicon, implanting impurity, and selectively etching and removing the impurity to form a gate electrode and polysilicon wirings, a step of forming an N type drain region and an N type source region in a self-aligning manner with respect to the gate electrode by lithography and ion implantation, a step of forming a P type drain region and a P type source region in a self-aligning manner with respect to the gate electrode by lithography and ion implantation, and a step of depositing an interlayer insulating film, selectively etching and removing the interlayer insulating film by lithography to form a contact hole for metal wirings, physically forming a metal film, selectively etching and removing the metal film by lithography to form metal wirings, depositing an insulating film, and selectively etching and removing the insulating film by lithography to form a protective film.
In the conventional semiconductor device, since the number of the required steps is large, there is a problem that the manufacturing cost is high and the cost of the chip can not be lowered.